Digital Design Engineer
Digital Design Engineer
Agile Analog is revolutionising the way Analog circuits are designed. Based in Cambridge but with the ability to work flexibly, we are growing quickly to become one of the world’s leading semiconductor IP companies. Using our innovative core technology, we are able to design circuits faster, to a higher quality, and on any silicon process.
We are disrupting methodologies that have been unchanged for generations and if you have that similar mindset with the desire to make an impact then play a part in our story.
As we embark on this journey of expansion, we are looking for Digital Design Engineers to join our team to help revolutionise the way that semiconductor IP is developed. You will be joining a highly experienced, proficient team of engineers and will need to be a good team player with a practical understanding of how to take engineering concepts to production.
As a Digital Design Engineer, you will be comfortable working across a range of digital and mixed signal IP developments, including low power and high-performance architectures. You will primarily be responsible for developing the design from concept to RTL implementation and synthesis, including front-end coding, scripting - developing flows at all phases of the digital design.
The role can accommodate candidates across a range of seniority and experience levels, as well as those with additional skills, particularly analog, software and automation skills. As part of a rapidly growing team, there are opportunities to utilise and develop your broader engineering skills in the process of develop our tools, infrastructure, IP and technical capabilities.
What you will be doing
- Digital and mixed signal microarchitecture definition and design
- RTL logic design, debug and functional verification
- Digital IP integration and verification in mixed signal IP developments
- Working collaboratively with technical leaders and engineers
- Developing the digital and mixed signal strategy and infrastructure
What we need from you:
- Hands-on experience and a successful track record of digital IC design using Verilog/ SystemVerilog HDL
- Experience of leading digital EDA tools for simulation, code debug & analysis etc
- Understanding of digital architecture trade-offs for power, performance and area.
- Understanding on asynchronous clock domains & multiple power domains in a mixed signal environment
- Understanding of synthesis timing constraints, static timing analysis and constraints development
- Strong scripting skills (ideally Python) and a working knowledge of automation, version management and continuous integration techniques
- Excellent communication and interpersonal skills
- Excellent time management and organisational skills
- Ability to inspire and empower others to deliver high quality IP within tight schedules.
Even better if you have one or more of:
- Experience of emulator and FPGA platforms
- UVM and formal verification experience – including development of assertions
- UPF and low power/ multiple power domain experience, particularly in a mixed signal environment
- Experience with logical equivalence checking
- Digital physical design including place & route, physical signoff, cell characterisation
- Analog/ mixed signal design environment
- DFT & ATPG experience
- Development of mixed signal IP
What we offer in return:
As well as the opportunity to really play a pivotal part in our success, we offer:
- A friendly, supportive and inclusive working environment
- Flexible work hours to fit around your personal commitments
- Hybrid Working
- Professional development and professional society membership
- Company share options
- 25 days’ annual leave with the option to purchase additional days
- Company pension scheme (with a salary sacrifice option)
- Private health insurance (including optical and dental cover)
- Life Assurance
- Cycle-to-work scheme
- Employee Assistance Programme – free wellbeing and health services
If the above role matches your experience, skills and motivations then we would love to hear from you.
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