Company

Qualcomm China

Job Area

Interns Group, Interns Group > Interim Engineering Intern - SW

General Summary

• Handle synthesis/DFT logic insertion and ATPG pattern generation.
• Handle physical design tasks from verilog netlist to GDS.
• Handle Chip/Block floorplan, PD implementation, include placement, CTS,PCTS,routing,timing analysis,SI analysis and IR-drop analysis.
• Timing fix and signoff with timing check tool Primetime.
• Finish DRC/ERC/PERC/LVS checks.
  
  
  

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