Company

Qualcomm India Private Limited

Job Area

Engineering Group, Engineering Group > Hardware Engineering

General Summary

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.
  
  
  

OR

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.

Job Overview

Person will be responsible for developing next generation SoCs for mobile products and its adjacencies. The role will require the candidate to understand and work on all aspects of VLSI development from micro architecture and platform architecture, front end design, and design convergence. The person is also responsible for overseeing physical design and verification aspects.

Job Description

• Full chip design for multi million gates SoC
• Digital design and development (RTL)
• Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification
• Manage IP dependencies, planning and tracking of all front end design related tasks
• Driving the project milestones across the design, verification and physical implementations
  
  
  

Minimum Qualifications

• Minimum 17 years of solid experience SoC design
• Developing architecture and micro-architecture from specs
• Understanding of various bus protocols AHB, AXI and peripherals like USB, SDCC
• Understanding of Memory controller designs and Microprocessors is an added advantage
• Understanding of Chip IO design and packaging is an added advantage
• Familiarity with various bus protocols like AHB, AXI is highly desired
• Ability to review top level test plans
• Expertise in Synopsys Design Compiler Synthesis and formal verification with Cadence LEC
• Working knowledge of timing closure is a must
• Should have good post silicon bring up and debug experience
• Should have good SoC integration exposure and its challenges
• Should have good exposure to design verification aspects
• Having SoC specification to GDS to commercialization experience is highly desired
• Needs to makes effective and timely decisions, even with incomplete information.
• Should possess a strong understanding of a particular technical area and accumulated significant experience in this area and other related areas.
• Provides direction, mentoring, and leadership to a small to medium sized groups.
• Should possess strong communication and leadership skills to ensure effective communication with Program
  
  
  

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