Qualcomm India is hiring DFT Engineers (8–16years) in Bangalore to deliver end‑to‑end DFT implementation for complex SoCs. You will work across scan insertion, ATPG, MBIST, and drive high‑quality test solutions in collaboration with RTL, DV, PD/STA and Test teams.

What you will do (core responsibilities)

• Own SoC / block DFT execution: scan insertion, validation, and sign‑off deliverables.
• Analyze and propose compression/DFT architecture suitable for the design and test goals.
• Drive ATPG pattern generation, coverage closure, and debug; meet aggressive coverage goals (static and at‑speed) as applicable.
• Resolve DFT DRCs, equivalence checks, and integration issues in partnership with front‑end teams.
• Own STA/constraints handoff for DFT and collaborate with STA teams to resolve timing violations.
• Deliver MBIST/RAMBIST architecture, insertion and validation, including debug support.

What we are looking for

• 8–16 years in DFT for production silicon with strong hands‑on in:
• Scan insertion, ATPG, MBIST
• Strong understanding of DFT rules/constraints, gate‑level validation and sign‑off flows.
• Proven ability to work independently, drive closure, and partner cross‑functionally.

Good to have

• ATE validation / bring‑up exposure.
• Experience in test diagnostics / yield debug support (if aligned to diagnostics tracks).

Why Qualcomm

Work on leading‑edge SoCs with opportunities to influence DFT architecture and methodology across high‑impact programs.